1. Field of the Invention
The present invention relates to a multi-layer circuit board for mounting an electronic element such as a semiconductor chip having connection electrodes arranged in the form of an area array or a semiconductor device having external connection terminals arranged in the form of an area array, such as in a regular lattice form or in a regular staggered manner.
2. Description of the Prior Art
In modern semiconductor devices, the logic devices are becoming highly functional and highly integrated, feature more inputs and outputs, and are being mounted ever more densely. Therefore, products have been produced to compensate for a lack of space for forming electrodes by arranging electrodes as an area array on the electrode-forming surface of a semiconductor chip.
FIG. 11 illustrates an example in which a semiconductor chip 4 is mounted on a circuit board 5 relying on an ordinary flip-chip connection. The semiconductor chip 4 has electrodes 6 arranged on the peripheral edges thereof. Circuit patterns 7 are connected to every electrode 6 on a single plane.
FIG. 12 illustrates the arrangement of lands 8 on a circuit board for mounting a semiconductor chip, and the arrangement of circuit patterns 7 drawn from the lands 8. In this example, the lands 8 are arranged in two sequences, each circuit pattern 7 is drawn running between the lands; i.e., the circuit pattern 7 is drawn from every land 8 on a single surface.
When the electrodes are arranged in many sequences in the longitudinal and transverse directions on the electrode-forming surface, however, it becomes no longer possible to take out the wirings toward the outer side from every land on the surface though it may vary depending upon the distance between the lands and the number of the lands.
In order to solve this problem, a method has been proposed according to which the circuit board for mounting a semiconductor chip is formed in many layers, and circuit patterns of the laminated circuit boards are suitably arranged to electrically connect all electrodes of the semiconductor chip to the circuit patterns. FIG. 13 illustrates an example where a semiconductor chip 4, on which the electrodes 6 are arranged as an area array, is mounted on a multi-layer circuit board. By using this multi-layer circuit board, it is possible to electrically connect every electrode 6 to the circuit patterns 7, 7a even though the semiconductor chip 4 has electrodes 6 arranged as an area array. In FIG. 13, reference numeral 7a denotes a circuit pattern of an inner layer, 5a to 5d denote first to fourth circuit boards, and reference numeral 9 denotes external connection terminals.
When the semiconductor chip having electrodes arranged as an area array is to be mounted on the circuit board, only about two circuit boards must be laminated one upon the other provided the number of the electrodes is not very large. However when the semiconductor chip has as may pins as, for example, 30.times.30 pins or 40.times.40 pins, six to ten circuit boards must be laminated one upon the other.
When a plurality of circuit boards, on which the circuit patterns are very densely formed, are to be laminated to make a multi-layer circuit board, there will be employed a high-density wiring method such as build-up method. However, these methods have serious problems in regard to yield of the products, reliability and the cost of production. That is, when many circuit boards are to be laminated one upon the other, the boards should be successively laminated in such a manner that electrical connection must be accomplished through the vias formed in each board between the circuit patterns and between the circuit patterns across the boards. Therefore, a high degree of precision would be required. However, at present, such methods do not offer a high degree of reliability. Furthermore, when many boards are laminated, it is required that none of the boards is defective, involving a further increased technical difficulty.